[coreboot-gerrit] Change in coreboot[master]: soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config

[Subrata Banik (Code Review)]

Attention is currently required from: Patrick Rudolph.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60728 )

Change subject: soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................

soc/intel/jsl: Replace dt `HeciEnabled` by `CSE disable` config

Lists of changes:

1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables CSE based on the `HeciEnabled`
chip config with `DISABLE_CSE_AT_PRE_BOOT` config.

Mainboards that choose to make CSE enable during boot don't select
`cse disable` config.

Signed-off-by: Subrata Banik 
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/smihandler.c
3 files changed, 1 insertion(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/60728/1

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 1b59ef0..1349f69 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -203,9 +203,6 @@
    #       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
    register "PchPmPwrCycDur" = "1"       # 1s

-	# Enable HECI
-	register "HeciEnabled" = "1"
-
    # Set xHCI LFPS period sampling off time, the default is 9ms.
    register "xhci_lfps_sampling_offtime_ms" = "9"

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 256fa06..f3e7240 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -142,10 +142,6 @@
    /* Gfx related */
    uint8_t SkipExtGfxScan;

-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
-
    /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
    uint8_t eist_enable;

diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c
index 2e38b68..18bcda4 100644
--- a/src/soc/intel/jasperlake/smihandler.c
+++ b/src/soc/intel/jasperlake/smihandler.c
@@ -16,11 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_jasperlake_config *config;
-
-	config = config_of_soc();
-
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
    	heci_disable();
 }