[coreboot-gerrit] Change in coreboot[master]: soc/intel/jsl: Add CdClock config

[Simon Yang (Code Review)]

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Kane Chen, Patrick Rudolph, Karthik Ramasubramanian.
Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jsl: Add CdClock config
......................................................................

Patch Set 14:

(1 comment)

File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/60009/comment/7547d2a5_3d3bd667 
PS14, Line 209: register "CdClock" = "0xff"
> Is this the default config in FSP? Are you planning to upload a follow-up change for Magolor?

=> Is this the default config in FSP?
Yes, 0xff is the default value of setting CdClock.
=> Are you planning to upload a follow-up change for Magolor?
No, I will leave it for ODM to adjust it.