[coreboot-gerrit] [S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Tarun.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email )

Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
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Patch Set 7:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81212/comment/2e119c3b_3677642f :
PS6, Line 42:  2 MB
> The goal is not to offer a one configuration fit all solution. Each project/board is free to use this feature as it fits the project. Also, SoC variants of a generation have a minimal cache size which we could rely on if it came to a point we wanted it to be the default of a soc configuration.
>
> But I don't believe it is going to make it to the default of a SoC configuration soon. I see it more like an option for a board where SPINOR constraints would be tight and without going through the burden of having to define a fixed `FSP_M_ADDR` and account for it.

OEMs/ODMs often face challenges when testing devices across a wide range of configurations (from Celeron to i7) using a unified AP FW image.  Hidden dependencies in the AP FW, such as minimum cache size requirements, can be easily overlooked, causing issues on low-end devices.

We need a way for OEMs/ODMs to statically assess whether their SoC designs meet the requirements for specific AP FW features, which i don't believe is the process.