Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36864 )
Change subject: soc/intel/cannonlake: Add chip config to override CPU flex ratio ......................................................................
Patch Set 6:
(2 comments)
I have read through the comments but still don't understand a lot of things:
Please explain why a higher ratio results in a lower speed.
Please explain in detail what the `CpuRatio` UPD actually does. How does it relate to `BootFrequency`?
Also, it seems to me that the measurements are void, because the currently simplified tsc_freq_mhz() implementation doesn't support "flex ratio". I think we should implement tsc_freq_mhz() correctly first, before jumping to any conclusions.
Additionally, for the interested reader: flex ratio adapts the maximum non-turbo ratio. And is mainly a feature to influence the TSC rate...
https://review.coreboot.org/c/coreboot/+/36864/2/src/soc/intel/cannonlake/ro... File src/soc/intel/cannonlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/36864/2/src/soc/intel/cannonlake/ro... PS2, Line 79: flex_ratio = rdmsr(MSR_FLEX_RATIO); If I understand the EDS correctly, this register's contents survive a reset. So the code here doesn't make much sense. It might read a stale value from a previous boot instead.
https://review.coreboot.org/c/coreboot/+/36864/2/src/soc/intel/cannonlake/ro... PS2, Line 80: if (CONFIG(OVERRIDE_CPU_FLEX_RATIO))
we could do that for sure but trying to leverage more from existing setting without writing […]
Can you please explain why it is faster with a lower clock speed?