Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/27974
Change subject: mediatek: Map SRAM as secure and cached memory ......................................................................
mediatek: Map SRAM as secure and cached memory
This patch changes the mapping of SRAM from non-secure to secure. Without this patch, mmu_config_range() can not work when MMU is enabled. The new config is still in non-secure cache since TTB section is allocated in SRAM which is mapped as non-secure.
BUG=b:80501386 TEST=Boots correctly on Kukui
Change-Id: Ia5b8716cfcca64d1d716a177225ea2f7ac2920a6 Signed-off-by: Tristan Shieh tristan.shieh@mediatek.com --- M src/soc/mediatek/common/include/soc/mmu_operations.h M src/soc/mediatek/common/mmu_operations.c 2 files changed, 11 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/27974/1
diff --git a/src/soc/mediatek/common/include/soc/mmu_operations.h b/src/soc/mediatek/common/include/soc/mmu_operations.h index b081690..79c3ea0 100644 --- a/src/soc/mediatek/common/include/soc/mmu_operations.h +++ b/src/soc/mediatek/common/include/soc/mmu_operations.h @@ -19,10 +19,11 @@ #include <arch/mmu.h>
enum { - DEV_MEM = MA_DEV | MA_S | MA_RW, - CACHED_MEM = MA_MEM | MA_NS | MA_RW, - SECURE_MEM = MA_MEM | MA_S | MA_RW, - UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, + DEV_MEM = MA_DEV | MA_S | MA_RW, + SECURE_CACHED_MEM = MA_MEM | MA_S | MA_RW, + SECURE_UNCACHED_MEM = MA_MEM | MA_S | MA_RW | MA_MEM_NC, + NONSECURE_CACHED_MEM = MA_MEM | MA_NS | MA_RW, + NONSECURE_UNCACHED_MEM = MA_MEM | MA_NS | MA_RW | MA_MEM_NC, };
extern unsigned char _sram_l2c[]; diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index b991084..78a1a44 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -26,16 +26,17 @@ mmu_init();
/* Set 0x0 to the end of 2GB dram address as device memory */ - mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); + mmu_config_range((void *)0, (uintptr_t)4U * GiB, DEV_MEM);
/* SRAM is cached */ - mmu_config_range(_sram, _sram_size, CACHED_MEM); + mmu_config_range(_sram, _sram_size, SECURE_CACHED_MEM);
/* L2C SRAM is cached */ - mmu_config_range(_sram_l2c, _sram_l2c_size, CACHED_MEM); + mmu_config_range(_sram_l2c, _sram_l2c_size, SECURE_CACHED_MEM);
/* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */ - mmu_config_range(_dma_coherent, _dma_coherent_size, UNCACHED_MEM); + mmu_config_range(_dma_coherent, _dma_coherent_size, + SECURE_UNCACHED_MEM);
mmu_enable(); } @@ -43,7 +44,7 @@ void mtk_mmu_after_dram(void) { /* Map DRAM as cached now that it's up and running */ - mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM); + mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM);
mtk_soc_after_dram(); }