Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46324 )
Change subject: soc/intel/broadwell: Revise SA lockdown sequence ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46324/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46324/5//COMMIT_MSG@10 PS5, Line 10: as per the Broadwell BIOS specification sequence order looks much different though
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... File src/soc/intel/broadwell/finalize.c:
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 36: REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0), Maybe you mixed up the numbers? This is 0x7*f*fc
https://review.coreboot.org/c/coreboot/+/46324/5/src/soc/intel/broadwell/fin... PS5, Line 38: REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */ BIOS spec places this before 0x6800.