[coreboot-gerrit] [M] Change in coreboot[master]: {cpu, security}: Stitch multiple microcodes per CPUID into CBFS

[Arthur Heymans (Code Review)]

Attention is currently required from: Himanshu Sahdev, Julius Werner, Lean Sheng Tan, Rizwan Qureshi, Subrata Banik, Tarun Tuli, Yu-Ping Wu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75357?usp=email )

Change subject: {cpu, security}: Stitch multiple microcodes per CPUID into CBFS
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Patch Set 14:

(1 comment)

File src/cpu/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/75357/comment/288b2a88_e849d593 :
PS10, Line 74: microcode-params := $(shell find "$(microcode-params-dir)" -type f | sed -e 's/.*///')
> > > > > On lighter note, ~10ms is still a big number, we are looking to optimize 2-3ms even. :P
> > > >
> > > > yeah on Chromebook every ms counts, I think this is also a very distinct differentiator of having coreboot instead of edk2 on Laptops ;)
> > >
> > > @Arthur, as i have moved the FIT microcode entry here for RO CBFS. should we need to add support for Top Swap 2nd FIT like https://review.coreboot.org/c/coreboot/+/75357/14/src/cpu/intel/fit/Makefile... ?
> >
> > fixing typo
> >
> > "don't we need to add support for Top Swap 2nd FIT as well like it had exited in other makefile https://review.coreboot.org/c/coreboot/+/75357/14/src/cpu/intel/fit/Makefile... ?"
>
> ping to get attention on the open question.

Hmm the topswap FIT points to a separate FMAP region iirc which has only once MCU in there that the RW-A/B writes to. I believe it should be unaffected.