[coreboot-gerrit] Change in coreboot[master]: nb/intel/ironlake: Add Generic Non-Core PCI device definition

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43739 )

Change subject: nb/intel/ironlake: Add Generic Non-Core PCI device definition
......................................................................

nb/intel/ironlake: Add Generic Non-Core PCI device definition

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/ironlake/early_init.c
M src/northbridge/intel/ironlake/ironlake.h
M src/northbridge/intel/ironlake/raminit.c
3 files changed, 9 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43739/1

diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index 2154478..24657d6 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -43,7 +43,7 @@
    /* bit 0 = disable multicore,
       bit 1 = disable quadcore,
       bit 8 = disable hyperthreading.  */
-	pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000);
+	pci_update_config32(QPI_NON_CORE, 0x80, 0xfffffefc, 0x10000);

u8 reg8;
    struct cpuid_result result;
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 06e0771..4f9db5b 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -48,6 +48,11 @@
 #include "hostbridge_regs.h"

/*
+ * Generic Non-Core Registers
+ */
+#define QPI_NON_CORE		PCI_DEV(QUICKPATH_BUS, 0, 0)
+
+/*
  * SAD - System Address Decoder
  */
 #define QPI_SAD			PCI_DEV(QUICKPATH_BUS, 0, 1)
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index b35d4c7..6c3a499 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3951,8 +3951,8 @@
    pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS);	// !!!!
    pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555);
    pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS);	// !!!!
-	pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0);	// !!!!
-	pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180);
+	pci_read_config32(QPI_NON_CORE, 0xd0);	// !!!!
+	pci_write_config32(QPI_NON_CORE, 0xd0, 0x180);
    gav(MCHBAR32(0x1af0));	// !!!!
    gav(MCHBAR32(0x1af0));	// !!!!
    MCHBAR32(0x1af0) = 0x1f020003;
@@ -4221,7 +4221,7 @@

MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8);
    MCHBAR32_AND_OR(0x2c80, 0, 0x53688);	// !!!!
-	pci_write_config32(PCI_DEV (0xff, 0, 0), 0x60, 0x20220);
+	pci_write_config32(QPI_NON_CORE, 0x60, 0x20220);
    MCHBAR16(0x2c20);	// !!!!
    MCHBAR16(0x2c10);	// !!!!
    MCHBAR16(0x2c00);	// !!!!