Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38341 )
Change subject: soc/intel/tigerlake: Update pci dev definition ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@9 PS9, Line 9: This change updates pci dev definition according to TGL EDS Dot/period at the end of sentences please.
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@10 PS9, Line 10: Add GSPI3 case in chip.c according to update pci dev definitions Ditto.
https://review.coreboot.org/c/coreboot/+/38341/9//COMMIT_MSG@10 PS9, Line 10: update updated
https://review.coreboot.org/c/coreboot/+/38341/9/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/38341/9/src/soc/intel/tigerlake/inc... PS9, Line 54: #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) Align with tabs?