Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43806 )
Change subject: haswell: Report only one HPET timer device ......................................................................
haswell: Report only one HPET timer device
VT-d checklist fails if there are multiple devices for a single HPET timer block, and if the bus/dev/fn differs between HPET devices.
Tested on Asrock B85M Pro4, verify VT-d check about HPET is successful.
Change-Id: I68fd074f5440c634ff3ed28c5d423835c81d33b9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi.c M src/southbridge/intel/lynxpoint/lpc.c 2 files changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43806/1
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 1df66bc..6a6a124 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -82,10 +82,8 @@ current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
- size_t i; - for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, 0); acpi_dmar_drhd_fixup(tmp, current); }
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 85fab4d..93b45d0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -370,10 +370,10 @@ u32 reg32; size_t i;
- /* Assign unique bus/dev/fn for each HPET */ + /* Assign the same bus/dev/fn for each HPET */ for (i = 0; i < 8; ++i) pci_write_config16(dev, LPC_HnBDF(i), - PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | 0);
/* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC);