[coreboot-gerrit] Change in coreboot[master]: Add configurable ramstage support for minimal PCI scanning

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )

Change subject: Add configurable ramstage support for minimal PCI scanning
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Patch Set 9:
> Patch Set 9:
> 2) Yes, it is about reducing boot times.
>
> Intel got some pretty good numbers by reducing what coreboot is doing. I can let them speak to that but the performance was compelling.

I am keen to see those numbers. In the past it was often overlooked that for ramstage, and resource allocation aspecially, having serial console enabled skews those numbers and makes results heavily dependent of the loglevel one has selected.

So let's make sure we get data from some practical setupruns, i.e. make sure serial console does not spew out everything.