Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40523 )
Change subject: soc/xeon_sp/skx: Define MSR PPIN related registers ......................................................................
soc/xeon_sp/skx: Define MSR PPIN related registers
These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Change-Id: I5e1de8bcb651fb8ae8b106db1978235b0dd84c47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40523 Reviewed-by: Frans Hendriks fhendriks@eltan.com Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/skx/include/soc/msr.h 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, but someone else must approve Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h index 2b1597b..dd05adc 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/msr.h @@ -96,4 +96,13 @@ #define EPB_ENERGY_POLICY_SHIFT 3 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT)
+/* MSR Protected Processor Inventory Number */ +#define MSR_PPIN_CTL 0x04e +#define MSR_PPIN_CTL_LOCK 0x1 +#define MSR_PPIN_CTL_ENABLE_SHIFT 1 +#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) +#define MSR_PPIN 0x04f +#define MSR_PPIN_CAP_SHIFT 23 +#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) + #endif /* _SOC_MSR_H_ */