Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42088 )
Change subject: WIP: soc/amd/picass: Write EIP to enable S3 ......................................................................
WIP: soc/amd/picass: Write EIP to enable S3
This now allows S3 to jump to boot block. The TSC value is still wrong.
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)...
SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170
coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000
BUG=b:147042464 TEST=Resume trembyle and see bootblock start.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 --- M src/soc/amd/picasso/bootblock/bootblock.c A src/soc/amd/picasso/include/soc/msr.h M src/soc/amd/picasso/root_complex.c 3 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42088/1
diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 1ff6896..9c268af 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -11,7 +11,12 @@ #include <cpu/amd/mtrr.h> #include <soc/southbridge.h> #include <soc/i2c.h> +#include <soc/msr.h> #include <amdblocks/amd_pci_mmconf.h> +#include <stdbool.h> +#include <acpi/acpi.h> + +asmlinkage void bootblock_pre_c_entry(void);
static void set_caching(void) { @@ -39,6 +44,22 @@ enable_cache(); }
+static void write_eip(void) +{ + bool s3_resume; + msr_t s3_resume_entry = { + .hi = (uint64_t)(uintptr_t)bootblock_pre_c_entry >> 32, + .lo = (uintptr_t)bootblock_pre_c_entry & 0xffffffff, + }; + + s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); + + /* Trigger the microcode to stash the CPU state and resume vector + * into the C6 save area. */ + if (!s3_resume) + wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); @@ -57,5 +78,7 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
+ write_eip(); + fch_early_init(); } diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h new file mode 100644 index 0000000..e7cdf9d --- /dev/null +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PICASSO_MSR_H__ +#define __PICASSO_MSR_H__ + +#define S3_RESUME_EIP_MSR 0xC00110E0 + +#endif /* __PICASSO_MSR_H__ */ diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index f621eea..8002048 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -11,6 +11,8 @@ #include <fsp/util.h> #include <stdint.h>
+#define RESET_VECTOR_SIZE 0x10 + static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); @@ -30,6 +32,13 @@ /* 1MB to top of low usable RAM */ ram_resource(dev, idx++, 1 * MiB / KiB, (mem_usable - 1 * MiB) / KiB);
+ /* HACK: Reserve bootblock */ + reserved_ram_resource( + dev, idx++, + (CONFIG_X86_RESET_VECTOR + RESET_VECTOR_SIZE - CONFIG_C_ENV_BOOTBLOCK_SIZE) + / KiB, + CONFIG_C_ENV_BOOTBLOCK_SIZE / KiB); + mmconf_resource(dev, MMIO_CONF_BASE);
if (!hob) {