[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Fix TSEG size computation

[Patrick Rudolph (Code Review)]

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30932 )

Change subject: soc/intel/fsp_broadwell_de: Fix TSEG size computation
......................................................................

soc/intel/fsp_broadwell_de: Fix TSEG size computation

The address bits 19:0 of TSEG_LIMIT read as zero, but are ignored on
comparison. The result is that the limit is effectively FFFFFh.

Add one MiB to the register value to make TSEG 8MiB instead of 7MiB.
Fixes a crash related to SMRR not matching the TSEG region.

Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/30932
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
Reviewed-by: Werner Zeh 
---
M src/soc/intel/fsp_broadwell_de/smmrelocate.c
1 file changed, 5 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
index f8f98c2..a58744e 100644
--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c
+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
@@ -220,9 +220,13 @@
     * encompasses the SMRAM range as well as the IED range.
     * However, the SMRAM available to the handler is 4MiB since the IEDRAM
     * lives TSEG_BASE + 4MiB.
+	 *
+	 * Note that address bits 19:0 are ignored and not compared.
+	 * The result is that BASE[19:0] is effectively 00000h and LIMIT is
+	 * effectively FFFFFh.
     */
    tseg_base = northbridge_get_base_reg(dev, TSEG_BASE);
-	tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT);
+	tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT) + 1 * MiB;
    tseg_size = tseg_limit - tseg_base;

params->smram_base = tseg_base;