Hello build bot (Jenkins), Caveh Jalali, Angel Pons, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39232
to look at the new patch set (#13).
Change subject: soc/intel/tigerlake: Enable Hybrid storage mode ......................................................................
soc/intel/tigerlake: Enable Hybrid storage mode
To use Optane memory, we need to set 2x2 PCIe lane mode while we need to set 1x4 PCIe lane mode for NVMe. The mode can be selected using the FIT tool at build time.
By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe lane mode if Optane memory is not detected and the mode is not 1x4 during boot up. The mode is saved in SPI NOR for next boot.
BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP from NVMe and Optane Check PCIe lane configuration.
Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae:
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/13