Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50574 )
Change subject: arch/x86/ioapic: clear full upper byte when writing ID register ......................................................................
arch/x86/ioapic: clear full upper byte when writing ID register
In all supported southbridges or SoCs I looked at and that aren't Cezanne (Intel ICH9, ICH10, 7 & 100 series PCH and AMD Bolton, Stoneyridge and Picasso), the ID register of the southbridge/PCH/FCH IOAPIC has the ID in bits 24-27 and the four bits above that all marked as reserved with a reset value of all zeros and the full register being both read and writable. On Cezanne however the IOAPIC ID is in bits 24-31 of the same register, so the topmost 4 bit's aren't reserved any more. To make sure that all 8 bits get actually set to the value we want them to have, mask those too. Since the default value is zero, masking those bits away won't change the value that gets written to the register after it gets or-ed with the IOAPIC ID shifted right by 24 bits.
Change-Id: Id730ed0abbe69d4679ec07910230cae1881c6c9a Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/arch/x86/ioapic.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/50574/1
diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 5e3e2af..b617476 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -71,7 +71,7 @@ printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); /* Set IOAPIC ID if it has been specified. */ io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | + (io_apic_read(ioapic_base, 0x00) & 0x00ffffff) | (ioapic_id << 24)); }