[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47234 )

Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47234/1//COMMIT_MSG@9 
PS1, Line 9: Testing
> Would be nice to elaborate on the testing. Could you break functionality […]

It's what has been described here: https://review.coreboot.org/c/coreboot/+/45578/8/src/mainboard/hp/folio_9480...

Essentially, not applying the IOBP settings for "port 0" made port 1 stop working. I don't have any Haswell ULT board nearby I could test things on, however.