Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40335 )
Change subject: src/arch/x86/acpi: Increase Max PCI bus count support ......................................................................
src/arch/x86/acpi: Increase Max PCI bus count support
This patch increase maximum bus end variable type to match latest SoC specification [Ice Lake EDS vol 1 chapter 3.18]
Change-Id: I90660c5cfd8af5bb40e36bb409e534541c786cae Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/40335/1
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6eded1d..ccc24db 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -104,7 +104,7 @@ }
int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end) + u16 seg_nr, u8 start, u16 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 644f52f..82faa8f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -871,7 +871,7 @@ int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); + u16 seg_nr, u8 start, u16 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current));