[coreboot-gerrit] [S] Change in coreboot[master]: inc/dev/pci_def.h: add definitions for RCEC EA Ext. Capbility

[Shuming Chu (Shuming) (Code Review)]

Attention is currently required from: Jonathan Zhang.

Hello Jonathan Zhang,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/69093

to review the following change.

Change subject: inc/dev/pci_def.h: add definitions for RCEC EA Ext. Capbility
......................................................................

inc/dev/pci_def.h: add definitions for RCEC EA Ext. Capbility

Root Complex Event Collector Endpoint Association Extended
Capability is defined in section 7.9.10 of PCIe 5.0 spec.

Add its Extended Capability ID, association bitmap for RCiEPs
register, and RCEC associated bus numbers register.

Signed-off-by: Jonathan Zhang 
Change-Id: I7bede8ed88304a2925e6e1e4128bcdd625ee0e53
---
M src/include/device/pci_def.h
1 file changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69093/1

diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index 64c1ac2..54bccc8 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -474,6 +474,9 @@
 #define PCI_EXP_SEC_LNK_CTL3	4	/* Link Control 3 */
 #define PCI_EXP_SEC_LANE_ERR_STATUS	8	/* Lane Error Status */

+/* Root Complex Event Collector Endpoint Association Extended Capability */
+#define  PCIE_EXT_CAP_RCECEA_ID	0x0007
+
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
 #define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
@@ -546,6 +549,10 @@
 #define  PCI_REBAR_CTRL_SIZE_MASK	 0xffff0000
 #define  PCI_REBAR_CTRL_SIZE_SHIFT	 16

+/* Root Complex Event Collector Endpoint Association */
+#define PCI_RCECEA_BITMAP 4
+#define PCI_RCECEA_BUSNUM 8
+
 /*
  * The PCI interface treats multi-function devices as independent
  * devices.  The slot/function address of each device is encoded