[coreboot-gerrit] [S] Change in coreboot[master]: src/mb/googe/rex/variants/rex0_ISH/overridetree: Enable ISH

[Jay Patel (Code Review)]

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal.

Jay Patel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74877 )

Change subject: src/mb/googe/rex/variants/rex0_ISH/overridetree: Enable ISH
......................................................................

src/mb/googe/rex/variants/rex0_ISH/overridetree: Enable ISH

This commit enables ISH and assigns ISH firmware file name.

BUG=
TEST="lspci" renders PCI ID 12.0 for Serial Controller: Device 7e45.
      It is also required that the ISH has been enabled using mFIT.

Signed-off-by: Jay Patel 
Change-Id: Idc8adaf62727d5bc00a36408e2850b56d83fe5f2
---
M src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/74877/1

diff --git a/src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb b/src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb
index ef517df..8e43bde 100644
--- a/src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0_ISH/overridetree.cb
@@ -269,6 +269,12 @@
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end	#PCIE9 SSD card
+		device ref ish on
+			chip drivers/intel/ish
+				register "firmware_name" = ""rex_ish.bin""
+				device generic 0 on end
+			end
+		end
    	device ref tbt_pcie_rp0 on end
    	device ref tbt_pcie_rp2 on end
    	device ref tcss_xhci on