[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add support to initialize DDR4 Memory

[Varun Joshi (Code Review)]

Varun Joshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )

Change subject: soc/intel/tigerlake: Add support to initialize DDR4 Memory
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Patch Set 22:

(3 comments)

https://review.coreboot.org/c/coreboot/+/39847/20/src/soc/intel/tigerlake/me... 
File src/soc/intel/tigerlake/meminit_tgl.c:

https://review.coreboot.org/c/coreboot/+/39847/20/src/soc/intel/tigerlake/me... 
PS20, Line 330: "
> \n

Done

https://review.coreboot.org/c/coreboot/+/39847/20/src/soc/intel/tigerlake/me... 
PS20, Line 332: "
> \n

Done

https://review.coreboot.org/c/coreboot/+/39847/21/src/soc/intel/tigerlake/me... 
File src/soc/intel/tigerlake/meminit_tgl.c:

https://review.coreboot.org/c/coreboot/+/39847/21/src/soc/intel/tigerlake/me... 
PS21, Line 299: print_spd_info((unsigned char *)blk->spd_array[0]);
              : 	print_spd_info((unsigned char *)blk->spd_array[1]);
              : 	print_spd_info((unsigned char *)blk->spd_array[2]);
              : 	print_spd_info((unsigned char *)blk->spd_array[3]);
> Yes that's correct too, I will add the loop.

Done