[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Add C620 p2sb.h

[Andrey Petrov (Code Review)]

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40919 )

Change subject: soc/intel/xeon_sp: Add C620 p2sb.h
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soc/intel/xeon_sp: Add C620 p2sb.h

Add p2sb.h that is shared by all currently supported Xeon SP CPUs.

Change-Id: Idcbff7ad587cb116897a953c079fb0a8b86cc2ed
Signed-off-by: Andrey Petrov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40919
Reviewed-by: Maxim Polyakov 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
A src/soc/intel/xeon_sp/include/soc/p2sb.h
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Maxim Polyakov: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/include/soc/p2sb.h b/src/soc/intel/xeon_sp/include/soc/p2sb.h
new file mode 100644
index 0000000..b90bc73
--- /dev/null
+++ b/src/soc/intel/xeon_sp/include/soc/p2sb.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <commonlib/helpers.h>
+
+/*
+ * Currently all known xeon-sp CPUs use C620 PCH. These definitions
+ * come from C620 datasheet (Intel Doc #336067-007US)
+ */
+
+#define HPTC_OFFSET			0x60
+#define HPTC_ADDR_ENABLE_BIT		(1 << 7)
+#define PCH_P2SB_EPMASK0		0xb0
+#define P2SB_SIZE			(16 * MiB)