mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38593 )
Change subject: sc7180: GPIO: Add I2S configuration for sc7180 ......................................................................
sc7180: GPIO: Add I2S configuration for sc7180
Configuring GPIO Pins as I2S mode for Audio speaker.
Change-Id: I681aa6d0d57671b0fd9b7bc88de6f2cc202a7af0 Signed-off-by: vsujithk vsujithk@codeaurora.org --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/include/soc/qi2s.h A src/soc/qualcomm/sc7180/qi2s.c 4 files changed, 80 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38593/1
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index ba1f675..6d6222b 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += qupv3_fw_config.c bootblock-y += qupv3_config.c bootblock-y += qcom_qup_se.c +bootblock-y += qi2s.c
################################################################################ verstage-y += timer.c @@ -27,7 +28,7 @@ verstage-y += qcom_qup_se.c verstage-y += qupv3_config.c verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c - +verstage-y += qi2s.c ################################################################################ romstage-y += cbmem.c romstage-y += timer.c @@ -45,7 +46,7 @@ romstage-y += qcom_qup_se.c romstage-y += qupv3_config.c romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c - +romstage-y += qi2s.c ################################################################################ ramstage-y += soc.c ramstage-y += timer.c @@ -61,7 +62,7 @@ ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c - +romstage-y += qi2s.c ################################################################################
CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b247d2d..83b22ba 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -18,6 +18,7 @@ #include <soc/mmu.h> #include <soc/qspi.h> #include <soc/qupv3_fw_config.h> +#include <soc/qi2s.h>
void bootblock_soc_init(void) { @@ -25,4 +26,5 @@ clock_init(); quadspi_init(25 * MHz); qupv3_fw_init(); + qi2s_init(); } diff --git a/src/soc/qualcomm/sc7180/include/soc/qi2s.h b/src/soc/qualcomm/sc7180/include/soc/qi2s.h new file mode 100644 index 0000000..ee02094a --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qi2s.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019-2020 Qualcomm Technologies. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_SC7180_QI2S_H__ +#define __SOC_QUALCOMM_SC7180_QI2S_H__ + +void qi2s_init(void); + + +#endif /* __SOC_QUALCOMM_SC7180_QI2S_H__ */ diff --git a/src/soc/qualcomm/sc7180/qi2s.c b/src/soc/qualcomm/sc7180/qi2s.c new file mode 100644 index 0000000..9661e55 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qi2s.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/clock.h> +#include <symbols.h> +#include <assert.h> +#include <gpio.h> +#include <string.h> +#include <soc/qi2s.h> + + +static void configure_gpios(void) +{ + + gpio_output(GPIO(49), 1); + gpio_output(GPIO(50), 1); + gpio_output(GPIO(51), 1); + gpio_output(GPIO(23), 1); + + gpio_configure(GPIO(23), 0, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + gpio_configure(GPIO(49), 1, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + gpio_configure(GPIO(50), 1, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + gpio_configure(GPIO(51), 1, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + +} + + +void qi2s_init() +{ + configure_gpios(); +} +