Attention is currently required from: Maulik V Vaghela, Ravindra, Sridhar Siricilla, Mark Hsieh, Patrick Rudolph. Hello build bot (Jenkins), Anil Kumar K, Maulik V Vaghela, Tim Wawrzynczak, Ravindra, Mark Hsieh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61586
to look at the new patch set (#6).
Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config ......................................................................
soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
The patch updates USB2_PORT_MAX macro to allow mark type_c flag and also renames the macro to USB2_PORT_MAX_TYPE_C to reflect the USB2 port is mapped to Type-C. Also, the patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in the device tree of Gimble and Gimble EVT. The macro modifies the USB2 configuration to indicate the port mapped to Type-C and sets Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2. This event is passed to USB3 upstream ports to upgrade back to super speed (USB3) after a downgrade during low power state. The change is done for Gimble DVT and EVT boards.
BUG=b:193287279 TEST=Built coreboot for Gimble and tested type A pen drive detect as super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d --- M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/soc/intel/alderlake/include/soc/usb.h 3 files changed, 5 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/61586/6