[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46261 )

Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
......................................................................

soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox

This SOC overrides the common PMC device and instantiates the PMC device
in the SSDT.  It needs to call the common PMC function to provide the
IPC mailbox method.

The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.

BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device in the
devicetree and disassemble the SSDT to ensure the RTD3 code is present.

Signed-off-by: Duncan Laurie 
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46261
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/pmc.c
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 507f871..e117842 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -50,6 +50,7 @@
    select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
    select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
    select SOC_INTEL_COMMON_BLOCK_HDA
+	select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
    select SOC_INTEL_COMMON_BLOCK_SA
    select SOC_INTEL_COMMON_BLOCK_SMM
    select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index dbf3671..c5a4ae5 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -13,6 +13,7 @@
 #include <drivers/intel/pmc_mux/chip.h>
 #include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/pmc_ipc.h>
 #include <intelblocks/rtc.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -119,6 +120,10 @@
    acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
    acpigen_write_resourcetemplate_footer();

+	/* Define IPC Write Method */
+	if (CONFIG(PMC_IPC_ACPI_INTERFACE))
+		pmc_ipc_acpi_fill_ssdt();
+
    acpigen_pop_len(); /* PMC Device */
    acpigen_pop_len(); /* Scope */