[coreboot-gerrit] Change in coreboot[master]: util/inteltool: ahci: add code for dumping config and SIR registers

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39560 )

Change subject: util/inteltool: ahci: add code for dumping config and SIR registers
......................................................................

util/inteltool: ahci: add code for dumping config and SIR registers

This adds the code required to dump config and SIR registers.

Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560
Reviewed-by: Felix Held 
Tested-by: build bot (Jenkins) 
---
M util/inteltool/ahci.c
1 file changed, 54 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c
index 09f6427..3a18993 100644
--- a/util/inteltool/ahci.c
+++ b/util/inteltool/ahci.c
@@ -60,6 +60,11 @@
 int print_ahci(struct pci_dev *ahci)
 {
    size_t ahci_registers_size = 0, i;
+	size_t ahci_cfg_registers_size = 0;
+	const io_register_t *ahci_cfg_registers;
+	size_t ahci_sir_offset = 0;
+	size_t ahci_sir_registers_size = 0;
+	const io_register_t *ahci_sir_registers;

if (!ahci) {
    	puts("No SATA device found");
@@ -76,6 +81,55 @@
    	ahci_registers_size = 0x400;
    }

+	printf("\n============= AHCI Configuration Registers ==============\n\n");
+	for (i = 0; i < ahci_cfg_registers_size; i++) {
+		switch (ahci_cfg_registers[i].size) {
+		case 4:
+			printf("0x%04x: 0x%08x (%s)\n",
+				ahci_cfg_registers[i].addr,
+				pci_read_long(ahci, ahci_cfg_registers[i].addr),
+				ahci_cfg_registers[i].name);
+			break;
+		case 2:
+			printf("0x%04x: 0x%04x     (%s)\n",
+				ahci_cfg_registers[i].addr,
+				pci_read_word(ahci, ahci_cfg_registers[i].addr),
+				ahci_cfg_registers[i].name);
+			break;
+		case 1:
+			printf("0x%04x: 0x%02x       (%s)\n",
+				ahci_cfg_registers[i].addr,
+				pci_read_byte(ahci, ahci_cfg_registers[i].addr),
+				ahci_cfg_registers[i].name);
+			break;
+		}
+	}
+
+	printf("\n============= SATA Initialization Registers ==============\n\n");
+	for (i = 0; i < ahci_sir_registers_size; i++) {
+		pci_write_byte(ahci, ahci_sir_offset, ahci_sir_registers[i].addr);
+		switch (ahci_sir_registers[i].size) {
+		case 4:
+			printf("0x%02x: 0x%08x (%s)\n",
+				ahci_sir_registers[i].addr,
+				pci_read_long(ahci, ahci_sir_offset),
+				ahci_sir_registers[i].name);
+			break;
+		case 2:
+			printf("0x%02x: 0x%04x     (%s)\n",
+				ahci_sir_registers[i].addr,
+				pci_read_word(ahci, ahci_sir_offset),
+				ahci_sir_registers[i].name);
+			break;
+		case 1:
+			printf("0x%02x: 0x%02x       (%s)\n",
+				ahci_sir_registers[i].addr,
+				pci_read_byte(ahci, ahci_sir_offset),
+				ahci_sir_registers[i].name);
+			break;
+		}
+	}
+
    const pciaddr_t ahci_phys = ahci->base_addr[5] & ~0x7ULL;
    printf("\n============= ABAR ==============\n\n");
    printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)ahci_phys);