[coreboot-gerrit] Change in coreboot[master]: HACK: Enable PCIe refclk 100M alone

[Qizhong Cheng (Code Review)]

Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48724 )

Change subject: HACK: Enable PCIe refclk 100M alone
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HACK: Enable PCIe refclk 100M alone

Don't pull into TOT. Thanks.  b/170703028
This patch is just to open the refclk of pcie during the coreboot stage for PCIe hardware compliance testing. If Alvis wants to continue to test pcie hardware, please cherry-pick the patch.
Set GPIO65 pinmux for PCIe function which is clkreq#.

Signed-off-by: mtk20626 
Change-Id: Ie0f73eda4259028efe1eacc7d6e3ed4c15bfb75f
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/include/soc/pcie.h
A src/soc/mediatek/mt8192/pcie.c
3 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48724/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 833dc2b..5e71df1 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -59,6 +59,7 @@
 ramstage-y += soc.c
 ramstage-y += spm.c
 ramstage-y += sspm.c
+ramstage-y += pcie.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
 ramstage-y += ufs.c
diff --git a/src/soc/mediatek/mt8192/include/soc/pcie.h b/src/soc/mediatek/mt8192/include/soc/pcie.h
new file mode 100644
index 0000000..dd8f7ab
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/pcie.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_PCIE_H
+#define SOC_MEDIATEK_MT8192_PCIE_H
+
+void mtk_pcie_prepare(void);
+
+#endif
diff --git a/src/soc/mediatek/mt8192/pcie.c b/src/soc/mediatek/mt8192/pcie.c
new file mode 100644
index 0000000..c41687b
--- /dev/null
+++ b/src/soc/mediatek/mt8192/pcie.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/pcie.h>
+
+#define REG_PCIE_CLKREQ_EN (void *)(GPIO_BASE + 0x380)
+
+void mtk_pcie_prepare(void)
+{
+	u32 ret;
+
+	/* set PCIe clkreq# for refclk 100M */
+	ret = read32(REG_PCIE_CLKREQ_EN);
+	write32(REG_PCIE_CLKREQ_EN, ret | 0x33);
+	setbits32(REG_PCIE_CLKREQ_EN, 0x33);
+}