[coreboot-gerrit] Change in coreboot[master]: [test only] USB2 DBC

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41691 )

Change subject: [test only] USB2 DBC
......................................................................

[test only] USB2 DBC

Signed-off-by: Kane Chen 
Change-Id: I32eae987827b8a5dbe13bc91e97a330291289f7b
---
M src/soc/intel/tigerlake/romstage/fsp_params.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41691/1

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index ede5059..19c73d2 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -198,6 +198,8 @@

soc_memory_init_params(m_cfg, config);
    mainboard_memory_init_params(mupd);
+	m_cfg->PlatformDebugConsent = 5;
+
 }

__weak void mainboard_memory_init_params(FSPM_UPD *mupd)