Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34897 )
Change subject: arch/x86: Simplified postcar WB MTRR setup ......................................................................
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Would this approach, if applied to all intel platforms, have some issues? Do we need UC holes between cbmem_top() and TSEG?
kindly take a look and read this entire topic https://review.coreboot.org/q/topic:%22dram_cache_wb%22+(status:open%20OR%20...) why we have dropped WB and moved to WP for intermediate caching (cbmem_top -16MB) to cbmem-top
So far I have not seen any numbers of __significant__ performance boost using intermediate caching or POSTCAR_STAGE=n. Point to 'cbmem -t' output with numbers better than 4ms, which equals to about 0.5% improvement in reaching the kernel. Maybe You have someone in mind who will approve all the added complexity in source this adds, high price for 0.5%. Definetly not going to be me hitting +2 but will defer from giving -2 too.
Other type of optimizations will yield much better results, but I anticipate Intel is not willing to shrink down their FSP but continue to try force open-source project to adapt to their bloated API? But that's all the politics for today. As for coreboot proper, sure, I have many ideas what you can do to reach kernel faster. I have no numbers. I have no code. At the moment I have also no interest to share those ideas until this postcar MTRR discussion reaches a closure.
Besides, that change of WB->WP might apply to TSEG region as well, so you can equally consider this commit as providing the region for WP instead of WB. Or WC instead of WB. The type does not matter as long as one type is satisfactory for the complete region.