Attention is currently required from: Jonathan Zhang.
Hello Jonathan Zhang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/69090
to review the following change.
Change subject: drivers/intel/fsp2_0/include/fsp: accomodate xeon_sp FSPX_CONFIG definitions ......................................................................
drivers/intel/fsp2_0/include/fsp: accomodate xeon_sp FSPX_CONFIG definitions
Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot.
Re-define in the common code.
Update coreboot code to use FSP_X_CONFIG consistently.
Tested=On OCP Delta Lake, boot up OS successfully.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 --- M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/soc/intel/xeon_sp/cpx/Makefile.inc D src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/cpx/upd_display.c M src/soc/intel/xeon_sp/skx/upd_display.c M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h 7 files changed, 37 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/69090/1
diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 8392a03..efda881 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -33,6 +33,16 @@ #include <FirmwareVersionInfo.h> #endif
+/* + * Intel FSPs of XEON server platforms define FSPX_CONFIG + * instead of FSP_X_CONFIG, which is expected by coreboot. + */ +#if CONFIG(XEON_SP_COMMON_BASE) +#define FSP_T_CONFIG FSPT_CONFIG +#define FSP_M_CONFIG FSPM_CONFIG +#define FSP_S_CONFIG FSPS_CONFIG +#endif + #pragma pack(pop)
#endif diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 0cd267b..d2a1583 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -16,8 +16,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cooperlake_sp
-CPPFLAGS_common += -include $(src)/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h - cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b
endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h b/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h deleted file mode 100644 index 55b2e99..0000000 --- a/src/soc/intel/xeon_sp/cpx/include/soc/fsp_upd.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _FSP_UPD_H_ -#define _FSP_UPD_H_ - -/* Rename the FSP UPD structs to what they were historically called on other platforms. */ -#define FSP_T_CONFIG FSPT_CONFIG -#define FSP_M_CONFIG FSPM_CONFIG -#define FSP_S_CONFIG FSPS_CONFIG - -#endif diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index efdce78..6ce5ef5 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -154,7 +154,7 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - FSPM_CONFIG *m_cfg = &mupd->FspmConfig; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; const struct device *dev; const config_t *config = config_of_soc();
diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c index ae5eeda..33807d3 100644 --- a/src/soc/intel/xeon_sp/cpx/upd_display.c +++ b/src/soc/intel/xeon_sp/cpx/upd_display.c @@ -12,8 +12,8 @@ const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { - const FSPM_CONFIG *new; - const FSPM_CONFIG *old; + const FSP_M_CONFIG *new; + const FSP_M_CONFIG *old;
old = &fspm_old_upd->FspmConfig; new = &fspm_new_upd->FspmConfig; @@ -31,8 +31,8 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - const FSPS_CONFIG *new; - const FSPS_CONFIG *old; + const FSP_S_CONFIG *new; + const FSP_S_CONFIG *old;
old = &fsps_old_upd->FspsConfig; new = &fsps_new_upd->FspsConfig; diff --git a/src/soc/intel/xeon_sp/skx/upd_display.c b/src/soc/intel/xeon_sp/skx/upd_display.c index 84105dd6..c718a58 100644 --- a/src/soc/intel/xeon_sp/skx/upd_display.c +++ b/src/soc/intel/xeon_sp/skx/upd_display.c @@ -32,8 +32,8 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { - const FSPS_CONFIG *new; - const FSPS_CONFIG *old; + const FSP_S_CONFIG *new; + const FSP_S_CONFIG *old;
old = &fsps_old_upd->FspsConfig; new = &fsps_new_upd->FspsConfig; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index 0de0fa1..066c2ae 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -553,7 +553,7 @@ /** Offset 0x01E0 **/ UINT8 ReservedMemoryInitUpd[16]; -} FSP_M_CONFIG; +} FSPM_CONFIG;
/** Fsp M UPD Configuration **/