[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Provide interface to update TCC offset

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30803 )

Change subject: soc/intel/cannonlake: Provide interface to update TCC offset
......................................................................

soc/intel/cannonlake: Provide interface to update TCC offset

This change provides an interface for canonlake to set TCC.
With this change, we can add code to update Tcc in devicetree.

BUG=b:122636962
TEST=Match the result from TAT UI

Change-Id: Ib54a118e4e409919e3e60112e4621a109404b16d
Signed-off-by: John Su 
Reviewed-on: https://review.coreboot.org/c/30803
Tested-by: build bot (Jenkins) 
Reviewed-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/cpu.c
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 27 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lijian Zhao: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index 9601863..534f87f 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -167,6 +167,26 @@
    wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }

+static void configure_thermal_target(void)
+{
+	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = dev->chip_info;
+	msr_t msr;
+
+	/* Set TCC activation offset if supported */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
+	}
+	msr = rdmsr(MSR_TEMPERATURE_TARGET);
+	msr.lo &= ~0x7f; /* Bits 6:0 */
+	msr.lo |= 0xe6; /* setting 100ms thermal time window */
+	wrmsr(MSR_TEMPERATURE_TARGET, msr);
+}
+
 /*
  * The emulated ACPI timer allows replacing of the ACPI timer
  * (PM1_TMR) to have no impart on the system.
@@ -264,4 +284,7 @@
 {
    if (mp_init_with_smm(cpu_bus, &mp_ops))
    	printk(BIOS_ERR, "MP initialization failure.\n");
+
+	/* Thermal throttle activation offset */
+	configure_thermal_target();
 }
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index ea781bc..866d9c8 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -67,6 +67,7 @@
 {
    int i;
    FSP_S_CONFIG *params = &supd->FspsConfig;
+	FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
    struct device *dev = SA_DEV_ROOT;
    config_t *config = dev->chip_info;

@@ -239,6 +240,9 @@
    	params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
    if (config->PchPmSlpAMinAssert)
    	params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
+
+	/* Set TccActivationOffset */
+	tconfig->TccActivationOffset = config->tcc_offset;
 }

/* Mainboard GPIO Configuration */