HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61554 )
Change subject: src/cpu: Get rid of unnecessary blank line {before,after} barce ......................................................................
src/cpu: Get rid of unnecessary blank line {before,after} barce
Change-Id: I9b710d279da6db9125519f58ecba109a4d9fa8e3 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/microcode/microcode.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/slot_1/l2_cache.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mtrr/mtrr.c 9 files changed, 0 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/61554/1
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index f20d446..5e5fa81 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -313,7 +313,6 @@ /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); clock = ratio * CPU_BCLK; diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 469bd25..674a115 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -206,7 +206,6 @@ struct ext_sig_entry *entry = (struct ext_sig_entry *)(ext_tbl + 1);
for (i = 0; i < ext_tbl->ext_sig_cnt; i++, entry++) { - if ((sig == entry->sig) && (pf & entry->pf)) { return ucode_updates; } diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 11899c6..9d11ef0 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -185,7 +185,6 @@ /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); clock = ratio * IRONLAKE_BCLK + ratio / 3; diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index f1d03c8..08548c5 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -286,7 +286,6 @@ /* Generate the remaining entries */ for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); clock = ratio * SANDYBRIDGE_BCLK; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9de6b38..42c5870 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -327,7 +327,6 @@
static void model_206ax_init(struct device *cpu) { - /* Clear out pending MCEs */ /* This should only be done on a cold boot */ mca_clear_status(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 72ece23..e66bf39 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -90,7 +90,6 @@ msr = rdmsr(IA32_PECI_CTL); msr.lo |= 1; wrmsr(IA32_PECI_CTL, msr); - }
#define PIC_SENS_CFG 0x1aa diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index 2a27316..fa43366 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -244,7 +244,6 @@ /* If OK then get the result from BBL_CR_ADDR */ msr = rdmsr(BBL_CR_ADDR); return (msr.lo >> 0x15); - }
/* Write data into the L2 controller register at address */ @@ -270,7 +269,6 @@ */
for (i = 0; i < v2; i++) { - u32 data1, data2; // Bits legend // data1 = ffffffff @@ -352,7 +350,6 @@ */ for (cache_setting = BBLCR3_L2_SIZE_256K; cache_setting <= BBLCR3_L2_SIZE_4M; cache_setting <<= 1) { - eax = bblcr3 | cache_setting; msr.lo = eax; wrmsr(BBL_CR_CTL3, msr); @@ -726,7 +723,6 @@ /* Write to all cache lines to initialize */
while (cache_size > 0) { - /* Each cache line is 32 bytes. */ cache_size -= 32;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 7780be2..bbdd598 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -329,7 +329,6 @@
udelay(10); } - }
static void wait_other_cpus_stop(struct bus *cpu_bus) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index f1d36da..bc4acc4 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -346,7 +346,6 @@ wrmsr(msr_index[i], fixed_msrs[i]); enable_cache(); fixed_mtrrs_hide_amd_rwdram(); - }
void x86_setup_fixed_mtrrs_no_enable(void)