[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure RP setting

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40262 )

Change subject: soc/intel/tigerlake: Configure RP setting
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Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40262/3/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/40262/3/src/soc/intel/tigerlake/fsp... 
PS3, Line 128: 		params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i];
> why is the opposite of the config setting? why not keep it uniform? i.e. […]

Yes please. Let's keep this as PcieRpLtrEnable.