Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40732 )
Change subject: mb/ocp/tiogapass: fix advansed _PAD_CFG_STRUCT macros in config ......................................................................
mb/ocp/tiogapass: fix advansed _PAD_CFG_STRUCT macros in config
If the current pad configuration can not be determined using standard macros from the gpio_defs.h [1], then the intelp2m utility generates "advanced" _PAD_CFG_STRUCT() macros. However, often this configuration in the vendor’s firmware is erroneous. Change the extended macros to standard ones taking into account the information based on the schematic diagram and the previous GPIO configuration for FSP-M [2].
[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h
Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/ocp/tiogapass/gpio.h 1 file changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/40732/1
diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h index 77ae5ff..594ea6f 100644 --- a/src/mainboard/ocp/tiogapass/gpio.h +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -120,7 +120,7 @@ /* GPP_F4 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ - _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, DEEP, OFF, DRIVER), /* GPP_F6 - GPIO */ PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 0, PLTRST, NONE), /* GPP_F7 - GPIO */ @@ -175,13 +175,13 @@ /* GPP_C9 - GPIO */ PAD_CFG_GPO_GPIO_DRIVER(GPP_C9, 1, DEEP, NONE), /* GPP_C10 - GPIO */ - _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_EDGE_BOTH | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C8, NONE, PLTRST, EDGE_BOTH, ACPI), /* GPP_C11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, DEEP, OFF, DRIVER), /* GPP_C12 - GPIO */ - _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, DEEP, OFF, DRIVER), /* GPP_C13 - GPIO */ - _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, DEEP, OFF, DRIVER), /* GPP_C14 - GPIO */ PAD_CFG_GPI_SCI(GPP_C14, NONE, PLTRST, LEVEL, NONE), /* GPP_C15 - GPIO */ @@ -296,7 +296,7 @@ /* GPD6 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD6, NONE, RSMRST, OFF, ACPI), /* GPD7 - GPIO */ - _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(ACPI) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, RSMRST, OFF, ACPI), /* GPD8 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPD8, NONE, RSMRST, OFF, ACPI), /* GPD9 - GPIO */ @@ -433,15 +433,15 @@ /* GPP_G11 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G11, NONE, DEEP, OFF, DRIVER), /* GPP_G12 - GPIO */ - _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G12, NONE, DEEP, OFF, DRIVER), /* GPP_G13 - GPIO */ - _PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G13, NONE, DEEP, OFF, DRIVER), /* GPP_G14 - GPIO */ - _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G14, NONE, DEEP, OFF, DRIVER), /* GPP_G15 - GPIO */ - _PAD_CFG_STRUCT(GPP_G15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G15, NONE, DEEP, OFF, DRIVER), /* GPP_G16 - GPIO */ - _PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER) | PAD_PULL(NONE)), + PAD_CFG_GPI_TRIG_OWN(GPP_G16, NONE, DEEP, OFF, DRIVER), /* GPP_G17 - ADR_COMPLETE */ PAD_CFG_NF_BUF_TRIG(GPP_G17, NONE, DEEP, NF1, RX_DISABLE, OFF), /* GPP_G18 - NMI# */