[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801dx/smihandler.c: Use <southbridge/intel/common/pmbase.h>

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61647 )

Change subject: sb/intel/i82801dx/smihandler.c: Use <southbridge/intel/common/pmbase.h>
......................................................................

sb/intel/i82801dx/smihandler.c: Use <southbridge/intel/common/pmbase.h>

Change-Id: Ic1b6db6ad1a61b575f009c9f5895bcfcbae301b7
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/i82801dx/smihandler.c
1 file changed, 29 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/61647/1

diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 575d1ba..107d58d 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -7,6 +7,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_def.h>
+#include <southbridge/intel/common/pmbase.h>
 #include "i82801dx.h"

#define DEBUG_SMI
@@ -32,9 +33,9 @@
 {
    u16 reg16;

-	reg16 = inw(pmbase + PM1_STS);
+	reg16 = read_pmbase16(PM1_STS);
    /* set status bits are cleared by writing 1 to them */
-	outw(reg16, pmbase + PM1_STS);
+	write_pmbase16(PM1_STS, reg16);

return reg16;
 }
@@ -51,7 +52,7 @@
    if (pm1_sts & (1 <<  4)) printk(BIOS_SPEW, "BM ");
    if (pm1_sts & (1 <<  0)) printk(BIOS_SPEW, "TMROF ");
    printk(BIOS_SPEW, "\n");
-	int reg16 = inw(pmbase + PM1_EN);
+	int reg16 = read_pmbase16(PM1_EN);
    printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
 }

@@ -63,9 +64,9 @@
 {
    u32 reg32;

-	reg32 = inl(pmbase + SMI_STS);
+	reg32 = read_pmbase32(SMI_STS);
    /* set status bits are cleared by writing 1 to them */
-	outl(reg32, pmbase + SMI_STS);
+	write_pmbase32(SMI_STS, reg32);

return reg32;
 }
@@ -104,9 +105,9 @@
 {
    u32 reg32;

-	reg32 = inl(pmbase + GPE0_STS);
+	reg32 = read_pmbase32(GPE0_STS);
    /* set status bits are cleared by writing 1 to them */
-	outl(reg32, pmbase + GPE0_STS);
+	write_pmbase32(GPE0_STS, reg32);

return reg32;
 }
@@ -179,9 +180,9 @@
 {
    u8 reg8;

-	reg8 = inb(pmbase + SMI_EN);
+	reg8 = read_pmbase8(SMI_EN);
    reg8 |= EOS;
-	outb(reg8, pmbase + SMI_EN);
+	write_pmbase8(SMI_EN, reg8);
 }

static void busmaster_disable_on_bus(int bus)
@@ -231,12 +232,12 @@
    u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;

/* First, disable further SMIs */
-	reg8 = inb(pmbase + SMI_EN);
+	reg8 = read_pmbase8(SMI_EN);
    reg8 &= ~SLP_SMI_EN;
-	outb(reg8, pmbase + SMI_EN);
+	write_pmbase8(SMI_EN, reg8);

/* Figure out SLP_TYP */
-	reg32 = inl(pmbase + PM1_CNT);
+	reg32 = read_pmbase32(PM1_CNT);
    printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
    slp_typ = acpi_sleep_from_pm1(reg32);

@@ -255,7 +256,7 @@
    case ACPI_S5:
    	printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");

-		outl(0, pmbase + GPE0_EN);
+		write_pmbase32(GPE0_EN, 0);

/* Should we keep the power state after a power loss?
    	 * In case the setting is "ON" or "OFF" we don't have
@@ -278,17 +279,17 @@
     * event again. We need to set BIT13 (SLP_EN) though to make the
     * sleep happen.
     */
-	outl(reg32 | SLP_EN, pmbase + PM1_CNT);
+	write_pmbase32(PM1_CNT, reg32 | SLP_EN);

/* In most sleep states, the code flow of this function ends at
     * the line above. However, if we entered sleep state S1 and wake
     * up again, we will continue to execute code in this function.
     */
-	reg32 = inl(pmbase + PM1_CNT);
+	reg32 = read_pmbase32(PM1_CNT);
    if (reg32 & SCI_EN) {
    	/* The OS is not an ACPI OS, so we set the state to S0 */
    	reg32 &= ~(SLP_EN | SLP_TYP);
-		outl(reg32, pmbase + PM1_CNT);
+		write_pmbase32(PM1_CNT, reg32);
    }
 }

@@ -300,14 +301,14 @@
    reg8 = apm_get_apmc();
    switch (reg8) {
    case APM_CNT_ACPI_DISABLE:
-		pmctrl = inl(pmbase + PM1_CNT);
+		pmctrl = read_pmbase32(PM1_CNT);
    	pmctrl &= ~SCI_EN;
-		outl(pmctrl, pmbase + PM1_CNT);
+		write_pmbase32(PM1_CNT, pmctrl);
    	break;
    case APM_CNT_ACPI_ENABLE:
-		pmctrl = inl(pmbase + PM1_CNT);
+		pmctrl = read_pmbase32(PM1_CNT);
    	pmctrl |= SCI_EN;
-		outl(pmctrl, pmbase + PM1_CNT);
+		write_pmbase32(PM1_CNT, pmctrl);
    	break;
    }
 }
@@ -326,7 +327,7 @@
    	// power button pressed
    	u32 reg32;
    	reg32 = (7 << 10) | (1 << 13);
-		outl(reg32, pmbase + PM1_CNT);
+		write_pmbase32(PM1_CNT, reg32);
    }
 }

@@ -341,10 +342,10 @@
 static void southbridge_smi_gpi(void)
 {
    u16 reg16;
-	reg16 = inw(pmbase + ALT_GP_SMI_STS);
-	outl(reg16, pmbase + ALT_GP_SMI_STS);
+	reg16 = read_pmbase16(ALT_GP_SMI_STS);
+	write_pmbase16(ALT_GP_SMI_STS, reg16);

-	reg16 &= inw(pmbase + ALT_GP_SMI_EN);
+	reg16 &= read_pmbase16(ALT_GP_SMI_EN);

mainboard_smi_gpi(reg16);

@@ -356,7 +357,7 @@
 {
    u32 reg32;

-	reg32 = inl(pmbase + SMI_EN);
+	reg32 = read_pmbase32(SMI_EN);

/* Are periodic SMIs enabled? */
    if ((reg32 & MCSMI_EN) == 0)
@@ -406,7 +407,7 @@
 {
    u32 reg32;

-	reg32 = inl(pmbase + SMI_EN);
+	reg32 = read_pmbase32(SMI_EN);

/* Are periodic SMIs enabled? */
    if ((reg32 & PERIODIC_EN) == 0)
@@ -461,7 +462,7 @@
    u32 smi_sts;

/* Update global variable pmbase */
-	pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	pmbase = lpc_get_pmbase();

/* We need to clear the SMI status registers, or we won't see what's
     * happening in the following calls.
@@ -470,7 +471,7 @@

/* Filter all non-enabled SMI events */
    // FIXME Double check, this clears MONITOR
-	// smi_sts &= inl(pmbase + SMI_EN);
+	// smi_sts &= read_pmbase32(SMI_EN);

/* Call SMI sub handler for each of the status bits */
    for (i = 0; i < 31; i++) {