Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44211 )
Change subject: soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress ......................................................................
soc/intel/cannonlake: Set FSP-M UPD Heci1BarAddress
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR address is overridden with 0xfed1a000. This causes HECI transactions to fail between FSP-M call and postcar.
BRANCH=puff TEST=Verified sending HECI commands before and after FSP-M call on hatch.
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 37f4d50..ac42e00 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -157,6 +157,9 @@ /* Configure VT-d */ tconfig->VtdDisable = 0;
+ /* Set HECI1 PCI BAR address */ + m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS; + mainboard_memory_init_params(mupd); }