Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46456 )
Change subject: soc/intel/cbnt: Stitch in ACMs in the coreboot image ......................................................................
Patch Set 11: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/46456/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46456/11//COMMIT_MSG@7 PS11, Line 7: soc nit: sec
https://review.coreboot.org/c/coreboot/+/46456/11/src/security/intel/txt/Kco... File src/security/intel/txt/Kconfig:
https://review.coreboot.org/c/coreboot/+/46456/11/src/security/intel/txt/Kco... PS11, Line 55: default 0x40000 if INTEL_CBNT_SUPPORT Is this a CBnT-specific constraint, or is this needed because it is Xeon-SP?
https://review.coreboot.org/c/coreboot/+/46456/11/src/security/intel/txt/Mak... File src/security/intel/txt/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/46456/11/src/security/intel/txt/Mak... PS11, Line 32: CbNT nit: CBnT