[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Support to initialize Memory

[Bora Guvendik (Code Review)]

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )

Change subject: soc/intel/tigerlake: Support to initialize Memory
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Patch Set 12:

(4 comments)

https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/in... 
PS12, Line 23: 		
Please make it 3 tabs to be consistent with the defines above/

https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/in... 
PS12, Line 100: mb_ddr4x_cfg 
ddr4x_cfg to have similar naming convention to lpddr4x_cfg above.

https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/in... 
PS12, Line 102: DQ_PER_CHANNEL
#define for this is missing.

https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/in... 
PS12, Line 110: DQS_PER_CHANNEL
#define for this is missing.