[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed

[Tim Chu (Code Review)]

Hello Philipp Deppenwiese, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Rudolph, Ryback Hung, Jonathan Zhang, Johnny Lin, Angel Pons, Morgan Jang, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48640

to look at the new patch set (#4).

Change subject: soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed
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soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed

Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.

Tested=Execute "dmidecode -t 4" to check max speed is correct.

Signed-off-by: Tim Chu 
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
---
M src/soc/intel/xeon_sp/cpx/ramstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48640/4