[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add option to disabble HyperTreading

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35208 )

Change subject: soc/intel/skylake: Add option to disabble HyperTreading
......................................................................

soc/intel/skylake: Add option to disabble HyperTreading

Needs test on KBL.

Change-Id: I3ebab68ff868c78105bb4b35abffb92f3ccf1705
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/romstage/romstage_fsp20.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35208/1

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 9cb8d45..8bf66f3 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -78,6 +78,11 @@
    select TSC_SYNC_MFENCE
    select UDELAY_TSC

+config FSP_HYPERTHREADING
+	bool "Enable HyperThreading"
+	depends on SOC_INTEL_KABYLAKE
+	default y
+
 config CPU_INTEL_NUM_FIT_ENTRIES
    int
    default 10
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index ecd1428..f3f8063 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -251,6 +251,7 @@
    	m_cfg->PchHpetDeviceNumber = 15;
    	m_cfg->PchHpetFunctionNumber = 0;
    }
+	m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING);
 }

static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,