[coreboot-gerrit] Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Meera Ravindranath (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Paul Menzel, Subrata Banik, Angel Pons.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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Patch Set 13:

(1 comment)

File src/mainboard/intel/adlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/d8e9def1_ede4c405 
PS13, Line 60: ADL_P_DDR5_2
> @meera, can you please address this review comment ? […]

Sure Subrata. Will do this.
@Furquan: Will push the new changes in a day. Facing some issues in getting the DDR5 board at our end to verify the changes.