Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48286 )
Change subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48286/18/src/soc/intel/common/block... File src/soc/intel/common/block/cpu/car/exit_car.S:
https://review.coreboot.org/c/coreboot/+/48286/18/src/soc/intel/common/block... PS18, Line 94: /* Reset CLOS selector to 0 */ : mov $IA32_PQR_ASSOC, %ecx : rdmsr : and $~IA32_PQR_ASSOC_MASK, %edx : wrmsr
Shouldn't we have the same logic here as in NEM programming, e.g., […]
Yes Tim, I think so. I was looking at following file. Comment captures that bits 33:32 are used in following MSR. So I think copying to edx was made purposefully for earlier programs as well.
src/include/cpu/x86/msr.h /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)