[coreboot-gerrit] New patch to review for coreboot: [DO NOT MERGE] riscv: Work around lowrisc's different page table format

[Jonathan Neuschäfer]

Jonathan Neuschäfer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17709

-gerrit

commit 712db2324809c87b544668eff16f7f0afab0ac23
Author: Jonathan Neuschäfer 
Date:   Sun Dec 4 07:57:48 2016 +0100

[DO NOT MERGE] riscv: Work around lowrisc's different page table format

See https://github.com/lowRISC/rocket/issues/3

Change-Id: I23b9cc16c105d11b84a9da4a737a653c991e9d72
    Signed-off-by: Jonathan Neuschäfer 
---
 src/arch/riscv/virtual_memory.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 26a0169..d9b0e84 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -138,7 +138,7 @@ pte_t pte_create(uintptr_t ppn, int prot, int user)
    	pte |= PTE_X;
    if (user)
    	pte |= PTE_U;
-	return pte;
+	return pte | 0x1f;
 }

// The current RISCV *physical* address space is this: