Jonathan Kollasch has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41687 )
Change subject: mb/supermicro/x9scl: Select IPMI_KCS ......................................................................
Patch Set 3: Code-Review+1
Patch Set 3:
Oh, looks like we can't really generalize it...
- X11SSM has AST1400, while X11SSM-F has AST2400 - detection done by SCU7C register (hw id and revision) in X11SSMPeiDriver
- X8SIE-F/X8SIL-F and X9SCL-F/X9SCM-F have WPCM450, while the non-F variants don't have the chip populated -> detection probably by some strap/gpio/id/...
Ofc we could do some runtime detection in both cases. While I don't expect any problems on the X11 series (where the pads are connected in both cases), I do expect GPIO floating due to unconnected pins on the non-F variants. -> The non-F variants need a different GPIO config. We still could make that possible by switching between two configs in `mainboard.c`.
I am not sure if we really want do make it that complicated in contrast of making the BMC boards variants.
I looked around a bit. I have strong indication that PCH GPIO 57 (GP_LVL2 bit 25 aka mask 0x02000000) is used on the X9SCL/X9SCM series to indicate the presence of a WPCM450 BMC w/ firmware (bit is 0), vs. a WPCM150 GPU (bit is 1). This is already configured as a GPIO in x9scl/gpio.c. I've confirmed by reading GP_LVL2 on both a X9SCM-F and X9SCL. I have some confidence that this GPIO pin is configured by differences in the bills of materials for the different X9SCL/X9SCM variants, and as such there's not much reason to worry that the GPIO is floating.
As I said before: as we're not (yet) turning the ipmi device on in the x9scl device tree, this all is not actually a problem, and does not block this change for me.