[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48640 )

Change subject: soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed
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soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed

Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.

Tested=Execute "dmidecode -t 4" to check max speed is correct.

Signed-off-by: Tim Chu 
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/xeon_sp/cpx/ramstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c
index deb9030..1e0ba00 100644
--- a/src/soc/intel/xeon_sp/cpx/ramstage.c
+++ b/src/soc/intel/xeon_sp/cpx/ramstage.c
@@ -1,8 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <fsp/api.h>
+#include <smbios.h>

int soc_fsp_multi_phase_init_is_enable(void)
 {
    return 0;
 }
+
+unsigned int smbios_cpu_get_max_speed_mhz(void)
+{
+	return 3900;
+}