[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36519 )

Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating
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Patch Set 12:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36519/12/src/soc/intel/cannonlake/c... 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/c/coreboot/+/36519/12/src/soc/intel/cannonlake/c... 
PS12, Line 134: PchUsb2PhySusPgEnable
> It's a good suggestion. […]

It looks like the FSP variable defaults to 1 though, which is something we can't do here.  If someone looked at the FSP BSF and saw it says default 1 they might not set it in coreboot.