14 Jan
2019
14 Jan
'19
12:43 p.m.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25603 )
Change subject: nb/intel/i945: Put stage cache in TSEG ......................................................................
Patch Set 37: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/25603/37/src/northbridge/intel/i945/stage_ca... File src/northbridge/intel/i945/stage_cache.c:
https://review.coreboot.org/#/c/25603/37/src/northbridge/intel/i945/stage_ca... PS37, Line 26: RESERVED_SMM_OFFSET is that identical to SMM_RESERVED_SIZE?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da
Gerrit-Change-Number: 25603
Gerrit-PatchSet: 37
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