[coreboot-gerrit] Change in coreboot[master]: soc/intel/tgl: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry

[Jamie Ryu (Code Review)]

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42790 )

Change subject: soc/intel/tgl: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry
......................................................................

soc/intel/tgl: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry

This is a W/A to avoid a communication issue with CSE Lite over Heci
interface. This will help to avoid boot failures with CSE Lite until
the permanent fix is available.

BUG=b:158643194
TEST=build and boot volteer with serial and non-serial image

Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42790/1

diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 3077c7f..a0b1e10 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -361,4 +361,4 @@
    }
 }

-BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL);