Surendranath R Gurivireddy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36519 )
Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating ......................................................................
Patch Set 12:
(5 comments)
https://review.coreboot.org/c/coreboot/+/36519/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36519/11//COMMIT_MSG@13 PS11, Line 13: So,disabled
So, disable …
Done
https://review.coreboot.org/c/coreboot/+/36519/11//COMMIT_MSG@15 PS11, Line 15: Added
Add
Done
https://review.coreboot.org/c/coreboot/+/36519/12/src/soc/intel/cannonlake/c... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/36519/12/src/soc/intel/cannonlake/c... PS12, Line 134: PchUsb2PhySusPgEnable
Should this be inverted (default enabled) so boards don't have to explicitly enable?
It's a good suggestion. I wanted to keep the same meaning/name as the corresponding FSP parameter to which this value is assigned. For Hatch, it's set to 1 by default. Please let me know if you still want it to be changed.
https://review.coreboot.org/c/coreboot/+/36519/5/src/soc/intel/cannonlake/ch... File src/soc/intel/cannonlake/chip.h:
https://review.coreboot.org/c/coreboot/+/36519/5/src/soc/intel/cannonlake/ch... PS5, Line 133: uint8_t PchUsb2PhySusPgEnable;
Add comment /* USB2 PHY power gating */
Done
https://review.coreboot.org/c/coreboot/+/36519/3/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/36519/3/src/soc/intel/cannonlake/fs... PS3, Line 277: params->PchUsb2PhySusPgEnable = 0;
This change is done based on the Intel's recommendation (Sighting is attached in the partner issue […]
Done