Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3515
-gerrit
commit 456be76331061a8af9750a4dc3e9de95bb0f6e7a Author: Stefan Reinauer reinauer@chromium.org Date: Mon May 20 16:23:40 2013 -0700
Add support to enable/disable builtin GbE
In case we are going to use this in future designs.
BUG=none TEST=none BRANCH=none
Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29 Signed-off-by: Stefan Reinauer reinauer@google.com Reviewed-on: https://gerrit.chromium.org/gerrit/55844 Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/northbridge/intel/haswell/pei_data.h | 3 ++- src/northbridge/intel/sandybridge/pei_data.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 280c73b..7c10e41 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -31,7 +31,7 @@ #define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 10 +#define PEI_VERSION 11
struct pei_data { @@ -53,6 +53,7 @@ struct pei_data uint8_t spd_addresses[4]; int boot_mode; int ec_present; + int gbe_enable; // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index fb56873..d317515 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -38,7 +38,7 @@ typedef struct { } pch_usb3_controller_settings;
typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 5 +#define PEI_VERSION 6
struct pei_data { @@ -61,6 +61,7 @@ struct pei_data uint8_t ts_addresses[4]; int boot_mode; int ec_present; + int gbe_enable; // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel